View M36DR432AD_122435.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M36DR432AD M36DR432BD
32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory and 4 Mbit (256Kb x16) SRAM, Multiple Memory Product
FEATURES SUMMARY s Multiple Memory Product - 1 bank of 32 Mbit (2Mb x16) Flash Memory - 1 bank of 4 Mbit (256Kb x16) SRAM s SUPPLY VOLTAGE - VDDF = VDDS =1.65V to 2.2V - VPPF = 12V for Fast Program (optional)
s s s
Figure 1. Package
ACCESS TIMES: 85ns, 100ns, 120ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE - Manufacturer Code: 0020h - Top Device Code, M36DR432AD: 00A0h - Bottom Device Code, M36DR432BD: 00A1h
FBGA
Stacked LFBGA66 (ZA) 12 x8mm
FLASH MEMORY s MEMORY BLOCKS - Dual Bank Memory Array: 4 Mbit, 28 Mbit - Parameter Blocks (Top or Bottom location)
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PROGRAMMING TIME - 10s by Word typical - Double Word Program Option
s s
ERASE SUSPEND and RESUME MODES 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION - Defectivity below 1ppm/year
s
ASYNCHRONOUS PAGE MODE READ - Page Width: 4 Words - Page Access: 35ns - Random Access: 85ns, 100ns, 120ns
s
s
DUAL BANK OPERATIONS - Read within one Bank while Program or Erase within the other - No delay between Read and Write operations
SRAM s 4 Mbit (256Kb x16)
s s
LOW VDDS DATA RETENTION: 1.0V POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS
s
BLOCK LOCKING - All blocks locked at Power up - Any combination of blocks can be locked - WPF for Block Lock-Down
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COMMON FLASH INTERFACE (CFI) - 64 bit Unique Device Identifier - 64 bit User Programmable OTP Cells
February 2003
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TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Address Inputs (A18-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Flash Reset/Power-Down (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VDDF Supply Voltage (1.65V to 2.2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VPPF Programming Voltage (11.4V to 12.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VSSF Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SRAM Chip Enable (ES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SRAM Output Enable (GS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VDDS Supply Voltage (1.65V to 2.2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 FLASH MEMORY COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. Flash Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Flash Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . 13 Flash Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash Standby.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Automatic Flash Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Dual Bank Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash Command Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Flash Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Set Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Quadruple Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Enter Bypass Mode Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Exit Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Double Word Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Quadruple Word Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bank Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. Flash Read Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 7. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 8. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 19 Flash Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reading a Block's Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 10. Flash Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Polling and Toggle Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 11. Polling and Toggle Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 12. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SRAM COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 13. Absolute Maximum Ratings(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 14. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 15. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 16. Flash DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 17. SRAM DC Characteristics (TA = -40 to 85C; VDDF = V DDS = 1.65V to 2.2V) . . . . . . . . 28 Figure 8. Flash Random Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 9. Flash Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 18. Flash Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 10. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 19. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 11. Flash Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 20. Flash Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 12. Flash Reset/Power-Down AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 21. Flash Reset/Power-Down AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 13. Flash Data Polling DQ7 AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 14. Flash Data Toggle DQ6, DQ2 AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 22. Flash Data Polling and Toggle Bits AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 15. Flash Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 16. Flash Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = VIL . . . . . . 38 Figure 18. SRAM Read AC Waveforms, ES or GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 19. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 23. SRAM Read AC Characteristics). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 20. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . . . . 40 Figure 21. SRAM Write AC Waveforms, WS Controlled with GS High . . . . . . . . . . . . . . . . . . . . . . 40 Figure 22. SRAM Write Cycle Waveform, UBS and LBS Controlled, G Low . . . . . . . . . . . . . . . . . 41 Figure 23. SRAM Write AC Waveforms, ES Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 24. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 24. SRAM Low V DDS Data Retention AC Waveforms, ES Controlled . . . . . . . . . . . . . . . . . 42 Table 25. SRAM Low VDDS Data Retention Characteristics (1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . 43 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 25. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Bottom View Package Outline 44 Table 26. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data . . . 44
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PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 APPENDIX A. BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 28. Bank A, Top Boot Block Addresses M36DR432AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 29. Bank B, Top Boot Block Addresses M36DR432AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 30. Bank B, Bottom Boot Block Addresses M36DR432BD . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 31. Bank A, Bottom Boot Block Addresses M36DR432BD . . . . . . . . . . . . . . . . . . . . . . . . . . 47 APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 32. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 33. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 34. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 35. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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SUMMARY DESCRIPTION The M36DR432AD/BD is a low-voltage Multiple Memory Product which combines two memory devices: a 32 Mbit (2Mbit x16) non-volatile Flash memory and a 4 Mbit SRAM. The memory is available in a Stacked LFBGA66 12x8mm - 8x8 active ball array, 0.8mm pitch package and supplied with all the bits erased (set to `1'). Figure 2. Logic Diagram
VDDF VPPF VDDS 21 A0-A20 WF EF GF RPF WPF E1S E2S GS WS UBS LBS M36DR432AD M36DR432BD 16 DQ0-DQ15
Table 1. Signal Names
A0-A17 A18-A20 DQ0-DQ15 VDDF VPPF VSSF VDDS VSSS NC Address Inputs Address Inputs for Flash Chip only Data Input/Outputs, Command Inputs Flash Power Supply Flash Optional Supply Voltage for Fast Program & Erase Flash Ground SRAM Power Supply SRAM Ground Not Connected Internally
Flash control functions EF GF WF RPF WPF Chip Enable Output Enable Write Enable Reset/Power-Down Write Protect input
SRAM control functions E1S E2S GS WS Chip Enable Chip Enable Output Enable Write Enable Upper Byte Enable Lower Byte Enable
VSSF
VSSS
UBS
AI07309b
LBS
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#1 1 2 3 4 5 6 7 8
#2
#3
#4
A NC
NC
NC
A20
A11
A15 A13 A12 VSSF NC
A14
NC
B DQ14
A16
A8 A9 DQ15 WS
A10
DQ7
C
WF
NC
DQ13
DQ6
DQ4
DQ5
D
VSSS
RPF DQ12
E2S
VDDS
VDDF
Figure 3. TFBGA Connections (Top view through package)
E WPF VPPF A19 DQ11
DQ10
DQ2
DQ3
F LBS GS
UBS
DQ9
DQ8
DQ0
DQ1
G
A18
A17 A7
A6
A3
A2
A1
E1S
H
NC
NC
NC
A5
A4
A0
EF
VSSF
GF
NC
NC
NC
M36DR432AD, M36DR432BD
AI90204
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SIGNAL DESCRIPTIONS See Figure 2 Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A17). Addresses A0-A17 are common inputs for the Flash and the SRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. During a write operation, the address inputs for the Flash memory are latched on the falling edge of the Flash Chip Enable (EF) or Write Enable (WF), whichever occurs last, whereas for the SRAM array they are latched on the falling edge of the SRAM Chip Enable lines (E1S or E2S) or Write Enable (WS). In the rest of the datasheet, only the Active Low SRAM Chip Enable line will be discussed. It will be referred to as ES. Address Inputs (A18-A20). Addresses A18-A20 are inputs for the Flash component only. They are latched during a write operation on the falling edge of Flash Chip Enable (EF) or Write Enable (WF), whichever occurs last. Data Input/Output (DQ0-DQ15). The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Write Bus operation. The input is data to be programmed in the Flash or SRAM memory array or a command to be written to the C.I. of the Flash memory. Both are latched on the rising edge of Flash Write Enable (WF) and, SRAM Chip Enable lines (ES) or Write Enable (WS). The output is data from the Flash memory array or SRAM array, the Electronic Signature Manufacturer or Device codes, the Block Protection status, the Configuration Register status or the Status Register Data (Polling bit DQ7, Toggle bits DQ6 and DQ2, Error bit DQ5 or Erase Timer bit DQ3) depending on the address. Outputs are valid when Flash Chip Enable (EF) and Output Enable (GF) or SRAM Chip Enable lines (ES) and Output Enable (GS) are active. The output is high impedance when both the Flash chip and the SRAM chip are deselected or the outputs are disabled and when Reset (RPF) is at VIL. Flash Chip Enable (EF). The Chip Enable input activates the Flash memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VIH the memory is deselected and the power consumption is reduced to the standby level. Flash Output Enable (GF). gates the outputs through the data buffers during a read operation.
When Output Enable, GF, is at V IH the outputs are High impedance. Flash Write Enable (WF). The Write Enable controls the Bus Write operation of the Flash memory's Command Interface. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each Flash block. When Write Protect is at VIL, the locked-down blocks cannot be locked or unlocked. When Write Protect is at VIH, the LockDown is disabled and the Locked-Down blocks can be locked or unlocked. Refer to Table 8, Read Protection Register. Flash Reset/Power-Down (RPF). The Reset/ Power-Down input provides hardware reset of the Flash memory, and/or Power-Down functions, depending on the Flash Configuration Register status. Reset or Power-Down of the memory is achieved by pulling RPF to VIL for at least tPLPH. The Reset/Power-Down function is set in the Configuration Register (see Set Configuration Register Command). If it is set to `0' the Reset function is enabled, if it is set to `1' the Power-Down function is enabled. After a Reset or Power-Up the power save function is disabled and all blocks are locked. The memory Command Interface is reset on Power Up to Read Array. Either Chip Enable or Write Enable must be tied to VIH during Power Up to allow maximum security and the possibility to write a command on the first rising edge of Write Enable. After a Reset, when the device is in Read, Erase Suspend Read or Standby, valid data will be output tPHQ7V1 after the rising edge of RPF. If the device is in Erase or Program, the operation will be aborted and the reset recovery will take a maximum of tPLQ7V. The memory will recover from Reset/Power-Down tPHQ7V2 after the rising edge of RPF. See Tables 18 and 19, and Figure 12. VDDF Supply Voltage (1.65V to 2.2V). VDDF provides the power supply to the internal core and I/O pins of the memory device. It is the main power supply for all operations (read, program and erase). VPPF Programming Voltage (11.4V to 12.6V). VPPF provides a high voltage power supply for fast factory programming. VPPF is required to use the Double Word and Quadruple Word Program commands. VSSF Ground. VSSF ground is the reference for the core supply. It must be connected to the system ground. SRAM Chip Enable (ES). The Chip Enable inputs for SRAM activate the memory control logic, input buffers and decoders. ES at V IH deselects
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the memory and reduces the power consumption to the standby level. ES can also be used to control writing to the SRAM memory array, while WS remains at VIL. It is not allowed to set EF at VIL and ES at VIL at the same time. SRAM Write Enable (WS). The Write Enable input controls writing to the SRAM memory array. WS is active Low. SRAM Output Enable (GS). The Output Enable gates the outputs through the data buffers during a read operation of the SRAM chip. GS is active Low. SRAM Upper Byte Enable (UBS). Enables the upper bytes for SRAM (DQ8-DQ15). UBS is active Low. SRAM Lower Byte Enable (LBS). Enables the lower bytes for SRAM (DQ0-DQ7). LBS is active Low. VDDS Supply Voltage (1.65V to 2.2V). VDDS is the SRAM power supply for all operations. Note: Each device in a system should have VDDF and VPPF decoupled with a 0.1F capacitor close to the pin. See Figure 7, AC Measurement Load Circuit. The PCB trace widths should be sufficient to carry the required VPPF program and erase currents.
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FUNCTIONAL DESCRIPTION The Flash and SRAM components have separate power supplies and grounds and are distinguished by three chip enable inputs: EF for the Flash memFigure 4. Functional Block Diagram
VDDF VPPF
ory and ES (E1S and E2S, respectively) for the SRAM.
EF GF WF RPF WPF Flash Memory 32 Mbit (2Mb x 16)
A18-A20 A0-A17
VDDS
VSSF
DQ0-DQ15
E1S E2S GS WS UBS LBS SRAM 4 Mbit (256Kb x 16)
VSSS
AI07310b
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Table 2. Main Operation Modes
Operation Mode Read Flash Memory Page Read Write Standby Reset/ Power-Down Output Disable Read Write SRAM Standby/Power Down EF VIL VIL VIL VIH X VIL GF VIL VIL VIH X X VIH WF VIH VIH VIL X X VIH RPF VIH VIH VIH VIH VIL VIH WPF VIH VIH VIH VIH VIH VIH VIL VIL VIH Any Flash mode is allowable X VIH Data Retention Output Disable Any Flash mode is allowable X Any Flash mode is allowable VIL X VIH X VIH VIH X Hi-Z Hi-Z X X X X VIH X Hi-Z Hi-Z ES GS WS UBS, LBS(1) DQ15-DQ0 Data Output Data Output Data Input Hi-Z Hi-Z Hi-Z Data out Word Read Data in Word Write Hi-Z
SRAM must be disabled SRAM must be disabled SRAM must be disabled Any SRAM mode is allowed Any SRAM mode is allowed Any SRAM mode is allowed VIL VIH X VIH VIL X VIL VIL X
Flash must be disabled Flash must be disabled
Note: 1. X = Don't care (V IL or VIH). 2. If UBS and LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBS and LBS separately.
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FLASH MEMORY COMPONENT The Flash Memory is a 32 Mbit (2Mbit x16) nonvolatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.65V to 2.2V VDDF supply for the circuitry and a 1.65V to 2.2V VDDQF supply for the Input/Output pins (in the stacked device, VDDF and VDDQF are tied internally). An optional 12V VPPF power supply is provided to speed up customer programming. The Flash device features an asymmetrical block architecture with an array of 71 blocks divided into two banks, Banks A and B, providing Dual Bank operations. While programming or erasing in Bank A, read operations are possible in Bank B or vice versa. Only one bank at a time is allowed to be in program or erase mode. The bank architecture is summarized in Table 3, and the Block Addresses are shown in Appendix A. The Parameter Blocks are located at the top of the memory address space for the M36DR432AD and, at the bottom for the M36DR432BD. Each block can be erased separately. Erase can be suspended, in order to perform either read or program in any other block, and then resumed. Each block can be programmed and erased over 100,000 cycles.
Program and Erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The Flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have two levels of protection. They can be individually locked and locked-down preventing any accidental programming or erasure. All blocks are locked at Power Up and Reset. The device includes a 128 bit Protection Register and a Security Block to increase the protection of a system's design. The Protection Register is divided into two 64 bit segments. The first segment contains a unique device number written by ST, while the second one is one-time-programmable by the user. The user programmable segment can be permanently protected. The Security Block, parameter block 0, can be permanently protected by the user. Figure 5, shows the Flash Security Block and Protection Register Memory Map.
Table 3. Flash Bank Architecture
Bank Size Bank A Bank B 4 Mbits 28 Mbits Parameter Blocks 8 blocks of 4 KWords Main Blocks 7 blocks of 32 KWords 56 blocks of 32 KWords
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Figure 5. Flash Security Block and Protection Register Memory Map
PROTECTION REGISTER 88h SECURITY BLOCK 85h 84h Parameter Block # 0 81h 80h Protection Register Lock 2 1 0 Unique device number User Programmable OTP
AI06185
Flash Bus Operations The following operations can be performed using the appropriate bus cycles: Flash Read Array (Random and Page Modes), Flash Write, Flash Output Disable, Flash Standby and Flash Reset/ Power-Down, see Table 2, Main Operation Modes. Flash Read. Flash Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register, the CFI, the Block Protection Status or the Configuration Register status. Read operation of the Flash memory array is performed in asynchronous page mode, that provides fast access time. Data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by A0-A1 address inputs. Read operations of the Electronic Signature, the Status Register, the CFI, the Block Protection Status, the Configuration Register status and the Security Code are performed as single asynchronous read cycles (Random Read). Both Flash Chip Enable EF and Flash Output Enable GF must be at VIL in order to read the output of the memory. Flash Write. Write operations are used to give commands to the memory or to latch Input Data to be programmed. A write operation is initiated when Chip Enable EF and Write Enable WF are at VIL with Output Enable GF at VIH. Addresses are latched on the falling edge of WF or EF whichever occurs last. Commands and Input Data are latched on the rising edge of WF or EF whichever occurs first. Noise pulses of less than 5ns typical on EF, WF and GF signals do not start a write cycle.
Flash Output Disable. The data outputs are high impedance when the Output Enable GF is at VIH with Write Enable WF at VIH. Flash Standby. The memory is in standby when Chip Enable EF is at V IH and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable GF or Write Enable WF inputs. Automatic Flash Standby. In Read mode, after 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while outputs still drive the bus. Flash Power-Down. The memory is in PowerDown when the Configuration Register is set for/ Power-Down and RPF is at VIL. The power consumption is reduced to the Power-Down level, and Outputs are high impedance, independent of the Chip Enable EF, Output Enable GF or Write Enable WF inputs. Dual Bank Operations. The Dual Bank allows data to be read from one bank of memory while a program or erase operation is in progress in the other bank of the memory. Read and Write cycles can be initiated for simultaneous operations in different banks without any delay. Status Register during Program or Erase must be monitored using an address within the bank being modified. Flash Command Interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller han13/52
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dles all timings and verifies the correct execution of the Program and Erase commands. Two bus write cycles are required to unlock the Command Interface. They are followed by a setup or confirm cycle. The increased number of write cycles is to ensure maximum data security. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation. The Command Interface is reset to Read mode when power is first applied or exiting from Reset. Command sequences must be followed exactly. Any invalid combination of commands will reset the device to Read mode Flash Read/Reset Command. The Read/Reset command returns the device to Read mode. One Bus Write cycle is required to issue the Read/Reset command and return the device to Read mode. Subsequent Read operations will read the addressed location and output the data. The write cycle can be preceded by the unlock cycles but it is not mandatory. Flash Read CFI Query Command. The Read CFI Query command is used to read data from the Common Flash Interface (CFI) and the Electronic Signature (Manufacturer or the Device Code, see Table 5). The Read CFI Query Command consists of one Bus Write cycle. Once the command is issued the device enters Read CFI mode. Subsequent Bus Read operations read the Common Flash Interface or Electronic Signature. Once the device has entered Read CFI mode, only the Read/Reset command should be used and no other. Issuing the Read/Reset command returns the device to Read mode. See Appendix B, Common Flash Interface, Tables 33, 34, and 35 for details on the information contained in the Common Flash Interface memory area. Auto Select Command. The Auto Select command uses the two unlock cycles followed by one write cycle to any bank address to setup the command. Subsequent reads at any address will output the Block Protection status, Protection Register and Protection Register Lock or the Configuration Register status depending on the levels of A0 and A1 (see Tables 6, 7 and 8). Once the Auto Select command has been issued only the Read/Reset command should be used and no other. Issuing the Read/Reset command returns the device to Read mode. Set Configuration Register Command. The Flash component contains a Configuration Register, see Table 7, Configuration Register. It is used to define the status of the Reset/PowerDown functions. The value for the Configuration Register is always presented on A0-A15, the other address bits are ignored. Address input A10 defines the status of the Reset/Power-Down functions. If it is set to `0' the Reset function is enabled, if it is set to `1' the Power-Down function is enabled. At Power Up the Configuration Register bit is set to `0'. The Set Configuration Register command is used to write a new value to the Configuration Register. The command uses the two unlock cycles followed by one write cycle to setup the command and a further write cycle to write the data and confirm the command. Program Command. The Program command uses the two unlock cycles followed by a write cycle to setup the command and a further write cycle to latch the Address and Data and start the Program Erase Controller. Read operations within the same bank output the Status Register after programming has started. Note that the Program command cannot change a bit set at '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole bank from '0' to '1'. If the Program command is used to try to set a bit from `0' to `1' Status Register Error bit DQ5 will be set to `1', only if VPPF is in the range of 11.4V to 12.6V. Double Word Program Command. This feature is offered to improve the programming throughput by writing a page of two adjacent words in parallel. The VPPF supply voltage is required to be from 11.4V to 12.6V for the Double Word Program command. The command uses the two unlock cycles followed by a write cycle to setup the command. A further two cycles are required to latch the address and data of the two Words and start the Program Erase Controller. The addresses must be the same except for the A0. The Double Word Program command can be executed in Bypass mode to skip the two unlock cycles. Note that the Double Word Program command cannot change a bit set at '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole bank from '0' to '1'. If the Double Word Program command is used to try to set a bit from `0' to `1' Status Register Error bit DQ5 will be set to `1'. Quadruple Word Program Command. The Quadruple Word Program command improves the programming throughput by writing a page of four adjacent words in parallel. The four words must differ only for the addresses A0 and A1. The VPPF supply voltage is required to be from 11.4V to 12.6V for the Quadruple Word Program command.
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M36DR432AD, M36DR432BD
The command uses the two unlock cycles followed by a write cycle to setup the command. A further four cycles are required to latch the address and data of the four Words and start the Program Erase Controller. The Quadruple Word Program command can be executed in Bypass mode to skip the two unlock cycles. Note that the Quadruple Word Program command cannot change a bit set to '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole bank from '0' to '1'. If the Quadruple Word Program command is used to try to set a bit from `0' to `1' Status Register Error bit DQ5 will be set to `1'. Enter Bypass Mode Command. The Bypass mode is used to reduce the overall programming time when large memory arrays need to be programmed. The Enter Bypass Mode command uses the two unlock cycles followed by one write cycle to set up the command. Once in Bypass mode, it is imperative that only the following commands be issued: Exit Bypass, Program, Double Word Program or Quadruple Word Program. Exit Bypass Mode Command. The Exit Bypass Mode command uses two write cycles to setup and confirm the command. The unlock cycles are not required. After the Exit Bypass Mode command, the device resets to Read mode. Program in Bypass Mode Command. The Program in Bypass Mode command can be issued when the device is in Bypass mode (issue a Enter Bypass Mode command). It uses the same sequence of cycles as the Program command with the exception of the unlock cycles. Double Word Program in Bypass Mode Command. The Double Word Program in Bypass Mode command can be issued when the device is in Bypass mode (issue a Enter Bypass Mode command). It uses the same sequence of cycles as the Double Word Program command with the exception of the unlock cycles. Quadruple Word Program in Bypass Mode Command. The Quadruple Word Program in Bypass Mode command can be issued when the device is in Bypass mode (issue a Enter Bypass Mode command). It uses the same sequence of cycles as the Quadruple Word Program command with the exception of the unlock cycles. Block Lock Command. The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Three Bus Write cycles are required to issue the Block Lock command. The first two bus cycles unlock the Command Interface. s The third bus cycle sets up the Block Lock command and latches the block address. The lock status can be monitored for each block using the Auto Select command. Table 10 shows the Lock Status after issuing a Block Lock command. The Block Lock bits are volatile, once set they remain set until a hardware reset or power-down/ power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block Locking, for a detailed explanation. Block Unlock Command. The Blocks Unlock command is used to unlock a block, allowing the block to be programmed or erased. Three Bus Write cycles are required to issue the Blocks Unlock command. s The first two bus cycles unlock the Command Interface. s The third bus cycle sets up the Block UnLock command and latches the block address. The lock status can be monitored for each block using the Auto Select command. Table 10 shows the lock status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. Block Lock-Down Command. A locked or unlocked block can be locked-down by issuing the Block Lock-Down command. A locked-down block cannot be programmed or erased, or have its protection status changed when WPF is Low, VIL. When WPF is High, V IH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Three Bus Write cycles are required to issue the Block Lock-Down command. s The first two bus cycles unlock the Command Interface. s The third bus cycle sets up the Block LockDown command and latches the block address. The lock status can be monitored for each block using the Auto Select command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 10 shows the Lock Status after issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explanation. Block Erase Command. The Block Erase command can be used to erase a block. It sets all the bits within the selected block to '1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the device will return to Read Array mode. It is not necessary to pre-pros
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gram the block as the Program/Erase Controller does it automatically before erasing. Six Bus Write cycles are required to issue the command. s The first two write cycles unlock the Command Interface. s The third write cycles sets up the command s the fourth and fifth write cycles repeat the unlock sequence s the sixth write cycle latches the block address and confirms the command. Additional Block Erase confirm cycles can be issued to erase other blocks without further unlock cycles. All blocks must belong to the same bank; if a new block belonging to the other bank is given, the operation is aborted. The additional Block Erase confirm cycles must be given within the DQ3 erase timeout period. Each time a new confirm cycle is issued the timeout period restarts. The status of the internal timer can be monitored through the level of DQ3, see Status Register section for more details. Once the command is issued the device outputs the Status Register data when any address within the bank is read. After the command has been issued the Flash Read/Reset command will be accepted during the DQ3 timeout period, after that only the Erase Suspend command will be accepted. On successful completion of the Block Erase command, the device returns to Read Array mode. Bank Erase Command. The Bank Erase command can be used to erase a bank. It sets all the bits within the selected bank to '1'. All previous data in the bank is lost. The Bank Erase command will ignore any protected blocks within the bank. If all blocks in the bank are protected then the Bank Erase operation will abort and the data in the bank will not be changed. It is not necessary to pre-program the bank as the Program/Erase Controller does it automatically before erasing. As for the Block Erase command six Bus Write cycles are required to issue the command. s The first two write cycles unlock the Command Interface. s The third write cycles sets up the command s the fourth and fifth write cycles repeat the unlock sequence s the sixth write cycle latches the block address and confirms the command. Once the command is issued the device outputs the Status Register data when any address within the bank is read. On successful completion of the Bank Erase command, the device returns to Read Array mode. Erase Suspend Command. The Erase Suspend command is used to pause a Block Erase operation. In a Dual Bank memory it can be used to read data within the bank where an Erase operation is in progress. It is also possible to program data in blocks not being erased. One bus write cycle is required to issue the Erase Suspend command. The Program/Erase Controller suspends the Erase operation within 20s of the Erase Suspend command being issued and bits 7, 6 and/ or 2 of the Status Register are set to `1'. The device is then automatically set to Read mode. The command can be addressed to any bank. During Erase Suspend the memory will accept the Erase Resume, Program, Read CFI Query, Auto Select, Block Lock, Block Unlock and Block LockDown commands. Erase Resume Command. The Erase Resume command can be used to restart the Program/ Erase Controller after an Erase Suspend command has paused it. One Bus Write cycle is required to issue the command. The command must be issued to an address within the bank being erased. The unlock cycles are not required. Protection Register Program Command. The Protection Register Program command is used to Program the Protection Register (One-Time-Programmable (OTP) segment and Protection Register Lock). The OTP segment is programmed 16 bits at a time. When shipped all bits in the segment are set to `1'. The user can only program the bits to `0'. Four write cycles are required to issue the Protection Register Program command. s The first two bus cycles unlock the Command Interface. s The third bus cycle sets up the Protection Register Program command. s The fourth latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. The OTP segment can be protected by programming bit 1 of the Protection Register Lock. The segment can be protected by programming bit 1 of the Protection Register Lock. Bit 1 of the Protection Register Lock also protects bit 2 of the Protection Register Lock. Programming bit 2 of the Protection Register Lock will result in a permanent protection of Parameter Block #0 (see Figure 5, Flash Security Block and Protection Register Memory Map). Attempting to program a previously
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protected Protection Register will result in a Status Register error. The protection of the Protection Table 4. Flash Commands
No of Cycles Bus Operations 1st Add X Data F0h AAh 2AAh 98h 55h 2nd Add Data 3rd Add Data 4th Add Data 5th Add Data 6th Add Data 7th Add Data
Register and/or the Security Block is not reversible.
Commands
1+ Read/Reset
Read Memory Array until a new write cycle is initiated. 555h F0h Read Memory Array until a new write cycle is initiated.
3+ 555h CFI Query Auto Select Set Configuration Register Program Double Word Program Quadruple Word Program Enter Bypass Mode Exit Bypass Mode Program in Bypass Mode Double Word Program in Bypass Mode Quadruple Word Program in Bypass Mode Block Lock Block Unlock Block Lock-Down Block Erase Bank Erase Erase Suspend Erase Resume 1+ 55h
Read CFI and Electronic Signature until a Read/Reset command is issued. 55h 555h 90h Read Protection Register, Block Protection or Configuration Register Status until a Read/Reset command is issued. 03h PD PD1 PD1 Read Data Polling or Toggle Bit until Program completes. PA2 PA2 PD2 PD2 PA3 PD3 PA4 PD4
3+ 555h
AAh 2AAh
4 555h 4 555h 5 555h 5 555h 3 555h 2 2 X X
AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh 90h A0h X PA
55h 55h 55h 55h 55h 00h PD
555h 555h 555h 555h 555h
60h CRD A0h 40h 50h 20h PA PA1 PA1
Read Data Polling or Toggle Bit until Program completes.
3
X
40h
PA1
PD1
PA2
PD2
3
X
50h
PA1
PD1 55h 55h 55h 55h 55h
PA2 555h 555h 555h 555h 555h
PD2 60h 60h 60h 80h 80h
PA3 BA BA BA 555h 555h
PD3 01h D0h 2Fh
PA4
PD4
4 555h 4 555h 4 555h 6+ 555h 6 555h 1 1 X BA
AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh B0h 30h
AAh 2AAh AAh 2AAh
55h 55h
BA BA
30h 10h
Read until Toggle stops, then read all the data needed from any Blocks not being erased then Resume Erase. Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time 55h PA C0h PA PD
Protection 4 555h Register Program
AAh 2AAh
Note: X = Don't Care, BA = Block Address, PA = Program address, PD = Program Data, CRD = Configuration Register Data. For Coded cycles address inputs A12-A20 are don't care.
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Table 5. Read Electronic Signature
Code Manufacturer Code M36DR432AD Device Code M36DR432BD
Note: X = Don't care.
Device
EF VIL VIL VIL
GF VIL VIL VIL
WF VIH VIH VIH
A0 VIL VIH VIH
A1 VIL VIL VIL
A7-A2 0 0 0
A8-A20 X X X
DQ15-DQ0 0020h 00A0h 00A1h
Table 6. Flash Read Block Protection
Block Status Locked Block Unlocked Block Locked-Down Block
Note: X = Don't care.
EF VIL VIL VIL
GF VIL VIL VIL
WF VIH VIH VIH
A0 VIL VIL VIL
A1 VIH VIH VIH
A20-A12 Block Address Block Address Block Address
A7-A2 0 0 0
Other Addresses X X X
DQ0 1 0 X
DQ1 0 0 1
DQ15-DQ2 0000h 0000h 0000h
Table 7. Configuration Register
RPF Function Reset Reset/Power-Down
Note: X = Don't care.
EF VIL VIL
GF VIL VIL
WF VIH VIH
A0 VIH VIH
A1 VIH VIH
A7-A2 0 0
Other Addresses X X
DQ10 0 1
DQ9-DQ0 DQ15-DQ11 Don't Care Don't Care
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Table 8. Read Protection Register
Word Lock Unique ID 0 Unique ID 1 Unique ID 2 Unique ID 3 OTP 0 OTP 1 OTP 2 OTP 3 EF VIL VIL VIL VIL VIL VIL VIL VIL VIL GF VIL VIL VIL VIL VIL VIL VIL VIL VIL WF VIH VIH VIH VIH VIH VIH VIH VIH VIH A20-A8 X X X X X X X X X A7-0 80h 81h 82h 83h 84h 85h 86h 87h 88h DQ15-8 XXh ID data ID data ID data ID data OTP data OTP data OTP data OTP data DQ7-3 00000b ID data ID data ID data ID data OTP data OTP data OTP data OTP data DQ2 Security prot.data ID data ID data ID data ID data OTP data OTP data OTP data OTP data DQ1 OTP prot.data ID data ID data ID data ID data OTP data OTP data OTP data OTP data DQ0 0 ID data ID data ID data ID data OTP data OTP data OTP data OTP data
Note: X= Don't care.
Table 9. Program, Erase Times and Program, Erase Endurance Cycles
M36DR432AD, M36DR432BD Parameter Min Parameter Block (4 KWord) Erase (Preprogrammed) Main Block (32 KWord) Erase (Preprogrammed) Bank Erase (Preprogrammed, Bank A) Bank Erase (Preprogrammed, Bank B) Chip Program (1) Chip Program (Double Word, VPPF = 12V) (1) Word Program (2) Double Word Program (VPPF = 12V) Quadruple Word Program (VPPF = 12V) Program/Erase Cycles (per Block) 100,000 100 100 100 Max 2.5 4 Typ 0.3 0.8 3 20 20 8 10 8 8 Typical after 100k W/E Cycles 1 3 6 30 25 Unit
s s s s s s s s s cycles
Note: 1. Excludes the time needed to execute the sequence for program command. 2. Same timing value if V PPF = 12V
Flash Block Locking The Flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has two levels of protection. s Lock/Unlock - this first level allows softwareonly control of block locking.
s
Lock-Down - this second level requires hardware interaction before locking can be changed.
The protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 10, defines all of the possible protection states (WPF, DQ1, DQ0). Reading a Block's Lock Status The lock status of every block can be read in the Auto Select mode of the device. Subsequent reads at the address specified in Table 6, will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when enter-
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M36DR432AD, M36DR432BD
ing Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. Locked State The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locked block will reset the device to Read Array mode. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command. Unlocked State Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command. Lock-Down State Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. LockedDown blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the WPF input pin. When WPF=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WPF=1 (VIH) the Lock-Down function is disabled (1,1,1) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while WPF remains High. When WPF is Low, blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WPF was High. Device reset or power-down resets all blocks, including those in Lock-Down, to the Locked state. Locking Operations During Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete.
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M36DR432AD, M36DR432BD
Table 10. Flash Lock Status
Current Protection Status(1) (WPF, DQ1, DQ0) Current State 1,0,0 1,0,1(2) 1,1,0 1,1,1 0,0,0 0,0,1(2) 0,1,1 Program/Erase Allowed yes no yes no yes no no After Block Lock Command 1,0,1 1,0,1 1,1,1 1,1,1 0,0,1 0,0,1 0,1,1 Next Protection Status(1) (WPF, DQ1, DQ0) After Block Unlock Command 1,0,0 1,0,0 1,1,0 1,1,0 0,0,0 0,0,0 0,1,1 After Block Lock-Down Command 1,1,1 1,1,1 1,1,1 1,1,1 0,1,1 0,1,1 0,1,1 After WPF transition 0,0,0 0,0,1 0,1,1 0,1,1 1,0,0 1,0,1 1,1,1 or 1,1,0 (3)
Note: 1. The lock status is defined by the write protect pin and by DQ1 (`1' for a locked-down block) and DQ0 (`1' for a locked block) as read in the Auto Select command with A1 = VIH and A0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WPF status. 3. A WPF transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
Flash Status Register The Status Register provides information on the current or previous Program or Erase operations. Bus Read operations from any address within the bank, always read the Status Register during Program and Erase operations. The various bits convey information about the status and any errors of the operation. The bits in the Status Register are summarized in Table 12, Status Register Bits. Refer to Tables 11 and 12 in conjunction with the following text descriptions. Data Polling Bit (DQ7). When Program operations are in progress, the Data Polling bit outputs the complement of the bit being programmed on DQ7. For a Double Word Program operation, it is the complement of DQ7 for the last Word written to the Command Interface. During an Erase operation, it outputs a '0'. After completion of the operation, DQ7 will output the bit last programmed or a '1' after erasing. Data Polling is valid and only effective during P/ E.C. operation, that is after the fourth WF pulse for programming or after the sixth WF pulse for erase. It must be performed at the address being programmed or at an address within the block being erased. See Figure 22 for the Data Polling flowchart and Figure 13 for the Data Polling waveforms. DQ7 will also flag an Erase Suspend by switching from '0' to '1' at the start of the Erase Suspend. In order to monitor DQ7 in the Erase Suspend mode an address within a block being erased must be
provided. DQ7 will output '1' if the read is attempted on a block being erased and the data value on other blocks. During a program operation in Erase Suspend, DQ7 will have the same behavior as in the normal program. Toggle Bit (DQ6). When Program or Erase operations are in progress, successive attempts to read DQ6 will output complementary data. DQ6 will toggle following the toggling of either GF or EF. The operation is completed when two successive reads give the same output data. The next read will output the bit last programmed or a '1' after erasing. The Toggle Bit DQ6 is valid only during P/E.C. operations, that is after the fourth WF pulse for programming or after the sixth WF pulse for Erase. DQ6 will be set to '1' if a read operation is attempted on an Erase Suspend block. When erase is suspended DQ6 will toggle during programming operations in a block different from the block in Erase Suspend. See Figure 16 for Toggle Bit flowchart and Figure 14 for Toggle Bit waveforms. Toggle Bit (DQ2). Toggle Bit DQ2, together with DQ6, can be used to determine the device status during erase operations. During Erase Suspend a read from a block being erased will cause DQ2 to toggle. A read from a block not being erased will output data. DQ2 will be set to '1' during program operation and to `0' in erase operation. If a read operation is addressed to a block where an erase error has occurred, DQ2 will toggle.
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Error Bit (DQ5). The Error Bit can be used to identify if an error occurs during a program or erase operation. The Error Bit is set to `1' when a program or erase operation has failed. When it is set to `0' the program or erase operation was successful. If any Program command is used to try to set a bit from `0' to `1' Status Register Error bit DQ5 will be set to `1', only if VPP is in the range of 11.4V to 12.6V. The Error Bit is reset by a Read/Reset command. Erase Timer Bit (DQ3). The Erase Timer bit is used to indicate the timeout period for an erase operation. When the last block Erase command has been entered to the Command Interface and it is waiting for the erase operation to start, the Erase Timer Bit is set to `0'. When the erase timeout period is finished, DQ3 returns to `1', (80s to 120s). DQ0, DQ1 and DQ4 are reserved for future use and should be masked. Table 11. Polling and Toggle Bits
Mode Program Erase Erase Suspend Read (in Erase Suspend block) Erase Suspend Read (outside Erase Suspend block) Erase Suspend Program DQ7 DQ7 0 DQ6 Toggle Toggle DQ2 1 N/A
1
1
Toggle
DQ7
DQ6
DQ2
DQ7
Toggle
1
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Table 12. Status Register Bits
DQ Name Logic Level '1' '0' 7 Data Polling DQ DQ '-1-0-1-0-1-0-1-' DQ 6 Toggle Bit '-1-1-1-1-1-1-1-' Definition Erase complete or erase block in Erase Suspend. Erase in progress Program complete or data of non erase block during Erase Suspend. Program in progress(2) Erase or Program in progress Program complete Erase complete or Erase Suspend on currently addressed block Program or Erase Error Program or Erase in progress Successive reads output complementary data on DQ6 while Programming or Erase operations are in progress. DQ6 remains at constant level when P/E.C. operations are completed or Erase Suspend is acknowledged. This bit is set to '1' in the case of Programming or Erase failure. Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase success. Note
'1' 5 4 Error Bit '0' Reserved '1' 3 Erase Time Bit '0'
Erase Timeout Period Expired
P/E.C. Erase operation has started. Only possible command entry is Erase Suspend An additional block to be erased in parallel can be entered to the P/E.C provided that it belongs to the same bank
Erase Timeout Period in progress Erase Suspend read in the Erase Suspended Block. Erase Error due to the currently addressed block (when DQ5 = '1'). Program in progress or Erase complete. Erase Suspend read on non Erase Suspend block.
'-1-0-1-0-1-0-1-' 2 Toggle Bit 1 DQ 1 0 Reserved Reserved
Indicates the erase status and allows to identify the erased block.
Note: 1. Logic level '1' is High, '0' is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations. 2. In case of double word program DQ7 refers to the last word input.
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SRAM COMPONENT The SRAM is a 4 Mbit (256Kb x16) low-power consumption memory array with low V DDS data retention. SRAM Operations The following operations can be performed using the appropriate bus cycles: Read Array, Write Array, Output Disable, Power Down (see Table 2). Read. Read operations are used to output the contents of the SRAM Array. The SRAM is in Read mode whenever Write Enable (WS) is at V IH with Output Enable (GS) at VIL, Chip Enable ES and UBS, LBS combinations are asserted. Valid data will be available at the output pins within tAVQV after the last stable address, provided that GS is Low and ES is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (t ELQV or tGLQV) rather than the address. Data out may be indeterminate at t ELQX and tGLQX, but data lines will always be valid at tAVQV (see Table 23, Figures 17 and 18). Write. Write operations are used to write data in the SRAM. The SRAM is in Write mode whenever the WS and ES pins are at VIL. Either the Chip Enable input (ES) or the Write Enable input (WS) must be de-asserted during address transitions for subsequent write cycles. Write begins with the concurrence of Chip Enable being active and WS at VIL. A Write begins at the latest transition
among ES going to VIL and WS going to VIL. Therefore, address setup time is referenced to Write Enable and Chip Enable as tAVWL and tAVEL respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the rising edge of ES or the rising edge of WS, whichever occurs first. If the Output is enabled (ES=VIL and GS=VIL), then WS will return the outputs to high impedance within t WLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for t DVEH before the rising edge of ES, whichever occurs first, and remain valid for t WHDX and tEHAX (see Table 24, Figure 20, 22, 24). Standby/Power-Down. The SRAM chip has a Chip Enable power-down feature which invokes an automatic standby mode (see Table 23, Figure 19) whenever either Chip Enable is de-asserted (ES=VIH). Data Retention. The SRAM data retention performances as V DDS go down to VDR are described in Table 25 and Figure 24. In ES controlled data retention mode, minimum standby current mode is entered when ES VDDS - 0.2V. Output Disable. The data outputs are high impedance when the Output Enable (GS) is at VIH with Write Enable (WS) at VIH.
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MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 13. Absolute Maximum Ratings(1)
Symbol TA TBIAS TSTG VIO (2) VDDF VDDS VPPF Parameter Ambient Operating Temperature (3) Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage SRAM Chip Supply Voltage Program Voltage Value -40 to 85 -40 to 125 -55 to 150 -0.5 to VDD(3)+0.5 -0.5 to 2.7 -0.5 to 2.4 -0.5 to 13 Unit C C C V V V V
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Minimum voltage may undershoot to -2V during transition and for less than 20ns. 2. Depends on range. 3. VDD = VDDS = V DDF.
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DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement
Conditions summarized in Table 14, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 14. Operating and AC Measurement Conditions
SRAM 70 Parameter Min VDDF Supply Voltage VDDS Supply Voltage VPPF Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages(1) Input and Output Timing Ref. Voltages(1)
Note: 1. VDD = VDDS = V DDF
Flash 85 100, 120 Units Max 2.2 12.6 85 30 4 0 to VDD VDD/2 Min 1.65 11.4 - 40 30 4 0 to VDD VDD/2 Max 2.2 12.6 85 V V V C pF ns V V
Max 2.2
Min 1.8 11.4
1.65
- 40 30
85 5 2
- 40
0 to VDD VDD/2
Figure 6. AC Measurement I/O Waveform
Figure 7. AC Measurement Load Circuit
VDD VDD
VDD VDD/2 0V
AI90206
25k DEVICE UNDER TEST 25k
Note: VDD means VDDF = VDDS
0.1F
CL = 50pF
CL includes JIG capacitance
Note: VDD means VDDF = VDDS
AI90207
Table 15. Device Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 12 15 Unit pF pF
Note: Sampled only, not 100% tested.
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Table 16. Flash DC Characteristics
Symbol ILI ILO ICC1 ICC2 ICC3 ICC4 (1) ICC5 (1) Parameter Input Leakage Current Output Leakage Current Supply Current (Read Mode) Supply Current (Power-Down) Supply Current (Standby) Supply Current (Program or Erase) Supply Current (Dual Bank) VPPF Supply Current (Program or Erase) VPPF Supply Current (Standby or Read) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage CMOS VPPF Supply Voltage (Program or Erase) IOL = 100A IOH = -100A VDD -0.1 -0.4 Double Word Program 11.4 VDD + 0.4 12.6 Test Condition 0V VIN VDD 0V VOUT VDD EF = VIL, GF = VIH, f = 6MHz RPF = VSS 0.2V EF = VDD 0.2V Word Program, Block Erase in progress Program/Erase in progress in one Bank, Read in the other Bank VPPF = 12V 0.6V VPPF VDD VPPF = 12V 0.6V -0.5 VDD - 0.4 3 2 10 10 Min Typ Max 1 5 6 10 50 20 Unit A A mA A A mA
13
26
mA
IPPF1
2 0.2 100
5 5 400 0.4 VDD + 0.4 0.1
mA A A V V V V V V
IPPF2 VIL VIH VOL VOH VPPF(2,3)
Note: 1. Sampled only, not 100% tested. 2. VPPF may be connected to 12V power supply for a total of less than 100 hrs. 3. For standard program/erase operation VPPF is don't care.
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Table 17. SRAM DC Characteristics (TA = -40 to 85C; VDDF = VDDS = 1.65V to 2.2V)
Symbol IOZ IIX IDDS Parameter Output Leakage Current Input Load Current VDD Standby Current Test Condition 0V VOUT VDDS, output disabled 0V VIN VDDS ES VDDS - 0.2V, VIN VDDS - 0.2V or VIN 0.2V, f=0 VDDS = 2.2V IOUT = 0 mA, f = fMAX = 1/tRC, CMOS levels VDDS = 2.2V IOUT = 0 mA, f = 0Hz CMOS levels VDDS = 1.65V VDDS = 2.2V VDDS = 1.65V IOL = 0.1A VDDS = 1.65V IOH = -0.1A 1.4 -0.5 1.4 Min -1 -1 Typ +1 1 1 Max +1 +1 10 Unit A A A
4 1
7 5 0.4 VDDS +0.2V 0.2
mA mA V V V V
IDD
Supply Current
VIL VIH VOL VOH
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Note: 1. IDDES and IDDWS are specified with device deselected. If device is read while in erase suspend, current draw is sum of IDDES and IDDR. If the device is read while in program suspend, current draw is the sum of IDDWS and IDDR. 2. VIN = VIL or VIH
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tAVAV VALID tAVQV tELQV tAXQX
A0-A20
EF tEHQZ tELQX tEHQX
Figure 8. Flash Random Read AC Waveforms
GF tGLQV tGLQX VALID tGHQX tGHQZ
DQ0-DQ15
AI07312
M36DR432AD, M36DR432BD
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Note: Write Enable (WF) = High.
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VALID VALID tELQV VALID VALID VALID tGLQV tAVQV tGHQX tEHQZ tAVQV1 VALID VALID VALID tEHQX VALID tGHQZ
AI07313
M36DR432AD, M36DR432BD
A2-A20
Figure 9. Flash Page Read AC Waveforms
A0-A1
EF
GF
DQ0-DQ15
M36DR432AD, M36DR432BD
Table 18. Flash Read AC Characteristics
M36DR432AD, M36DR432BD Symbol Alt Parameter Test Condition Min tAVAV tAVQV tAVQV1 tELQX (1) tELQV (2) tGLQX (1) tGLQV (2) tEHQX tEHQZ (1) tGHQX tGHQZ (1) tAXQX tRC tACC tPAGE tLZ tCE tOLZ tOE tOH tHZ tOH tDF tOH Address Valid to Next Address Valid Address Valid to Output Valid (Random) Address Valid to Output Valid (Page) Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Transition to Output Transition EF = VIL, GF = VIL EF = VIL, GF = VIL EF = VIL, GF = VIL GF = VIL GF = VIL EF = VIL EF = VIL GF = VIL GF = VIL EF = VIL EF = VIL EF = VIL, GF = VIL 0 0 20(3) 0 0 20(3) 0 25 0 0 25(3) 0 25 0 35 0 85(3) 0 25 0 35 85(3) 85(3) 30(3) 0 100 0 35 85 Max Min 100 100 35 0 120 100 Max Min 120 120 45 120 Max ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. GF may be delayed by up to tELQV - tGLQV after the falling edge of EF without increasing tELQV. 3. To be characterized.
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Figure 10. Flash Write AC Waveforms, Write Enable Controlled
tAVAV A0-A20 VALID tWLAX tAVWL EF tELWL GF tGHWL WF tWHWL tDVWH DQ0-DQ15 VALID tWHDX tWLWH tWHGL tWHEH
VDDF tVDHEL
AI07314
Note: Addresses are latched on the falling edge of WF, Data is latched on the rising edge of WF.
Table 19. Flash Write AC Characteristics, Write Enable Controlled
M36DR432AD, M36DR432BD Symbol Alt Parameter Min tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tVDHEL tWHGL tPLQ7V tVCS tOEH tWC tCS tWP tDS tDH tCH Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High 85(1) 0 50(1) 40(1) 0 0 30 0 50 0 50 30 15 85 Max Min 100 0 50 50 0 0 30 0 50 0 50 30 15 100 Max Min 120 0 50 50 0 0 30 0 50 0 50 30 15 120 Max ns ns ns ns ns ns ns ns ns ns s ns s Unit
tWPH Write Enable High to Write Enable Low tAS tAH Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low VDD High to Chip Enable Low Write Enable High to Output Enable Low RPF Low to Reset Complete During Program/Erase
Note: 1. To be characterized.
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M36DR432AD, M36DR432BD
Figure 11. Flash Write AC Waveforms, Chip Enable Controlled
tAVAV A0-A20 VALID tELAX tAVEL WF tWLEL GF tGHEL EF tEHEL tDVEH DQ0-DQ15 VALID tEHDX tELEH tEHGL tEHWH
VDDF tVDHWL
AI07315
Note: Addresses are latched on the falling edge of EF, Data is latched on the rising edge of EF.
Table 20. Flash Write AC Characteristics, Chip Enable Controlled
M36DR432AD, M36DR432BD Symbol Alt Parameter Min tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tVDHWL tEHGL tPLQ7V tVCS tOEH tWC tWS tCP tDS tDH tWH tCPH tAS tAH Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low VDD High to Write Enable Low Chip Enable High to Output Enable Low RPF Low to Reset Complete During Program/Erase 85(1) 0 50(1) 40(1) 0 0 30 0 50 0 50 30 15 85 Max Min 100 0 50 50 0 0 30 0 50 0 50 30 15 100 Max Min 120 0 50 50 0 0 30 0 50 0 50 30 15 120 Max ns ns ns ns ns ns ns ns ns ns s ns s Unit
Note: 1. To be characterized
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M36DR432AD, M36DR432BD
Figure 12. Flash Reset/Power-Down AC Waveform
READ PROGRAM / ERASE
WF
DQ7
VALID
DQ7
VALID
RPF tPLPH tPHQ7V tPLQ7V
AI07316
Table 21. Flash Reset/Power-Down AC Characteristics
M36DR432AD, M36DR432BD Symbol Alt Parameter Test Condition Min tPHQ7V1 RPF High to Data Valid (Read Mode) RPF High to Data Valid (Reset/Power-Down enabled) RPF Low to Reset Complete tRP RPF Pulse Width During Program During Erase 50 85 Max 150 Min 100 Max 150 Min 120 Max 150 ns Unit
tPHQ7V2
50 10 20 50
50 10 20 50
50 10 20
s s s ns
tPLQ7V tPLPH
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A0-A20 ADDRESS (WITHIN BLOCKS) tAVQV tELQV
EF tEHQ7V
GF tGLQV
Figure 13. Flash Data Polling DQ7 AC Waveforms
WF tWHQ7V DQ7 VALID
DQ7
DQ0-DQ6/ DQ8-DQ15
IGNORE tQ7VQV
VALID
M36DR432AD, M36DR432BD
LAST WRITE CYCLE OF PROGRAM OR ERASE INSTRUCTION
DATA POLLING READ CYCLES
DATA POLLING (LAST) CYCLE
MEMORY ARRAY READ CYCLE
AI07317
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VALID tEHQV tAVQV tELQV tGLQV tWHQV STOP TOGGLE VALID IGNORE VALID DATA TOGGLE READ CYCLE MEMORY ARRAY READ CYCLE
AI06196
M36DR432AD, M36DR432BD
A0-A20
EF
GF
Figure 14. Flash Data Toggle DQ6, DQ2 AC Waveforms
WF
DQ6,DQ2
DQ0-DQ1,DQ3-DQ5, DQ7-DQ15
LAST WRITE CYCLE OF PROGRAM OF ERASE INSTRUCTION
DATA TOGGLE READ CYCLE
Note: All other timings are as a normal Read cycle.
M36DR432AD, M36DR432BD
Table 22. Flash Data Polling and Toggle Bits AC Characteristics
Symbol Parameter M36DR432AD, M36DR432BD Min Write Enable High to DQ7 Valid (Program, WF Controlled) tWHQ7V Write Enable High to DQ7 Valid (Block Erase, WF Controlled) Chip Enable High to DQ7 Valid (Program, EF Controlled) tEHQ7V tQ7VQV tWHQV Chip Enable High to DQ7 Valid (Block Erase, EF Controlled) Q7 Valid to Output Valid (Data Polling) Write Enable High to Output Valid (Program) Write Enable High to Output Valid (Block Erase) Chip Enable High to Output Valid (Program) Chip Enable High to Output Valid (Block Erase) 8 0.8 8 0.8 0.8 8 0.8 4 100 4 0 100 4 100 4 s s s ns s s s s 8 Max 100 s Unit
tEHQV
Note: All other timings are defined in Read AC Characteristics
Figure 15. Flash Data Polling Flowchart
Figure 16. Flash Data Toggle Flowchart
START
START READ DQ5 & DQ6
READ DQ5 & DQ7 at VALID ADDRESS
DQ7 = DATA NO NO
YES
DQ6 = TOGGLES YES NO
NO
DQ5 =1 YES READ DQ7
DQ5 =1 YES READ DQ6
DQ7 = DATA NO FAIL
YES
DQ6 = TOGGLES YES PASS FAIL
NO
PASS
AI06197
AI06198
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Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V IL
tAVAV A0-A17 tAVQV tAXQX VALID
DQ0-DQ15
DATA VALID
DATA VALID
AI90217
Note: ES = Low, GS = Low, WS = High.
Figure 18. SRAM Read AC Waveforms, ES or GS Controlled
tAVAV A0-A17 tAVQV tELQV ES tELQX tBLQV UBS, LBS tBLQX tGLQV GS tGLQX DQ0-DQ15 DATA VALID
AI07311
VALID tAXQX tEHQZ
tBHQZ
tGHQZ
Note: Write Enable (WS) = High.
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Figure 19. SRAM Standby AC Waveforms
ES tPU tPD
IDD
AI07320
Table 23. SRAM Read AC Characteristics)
SRAM Symbol Alt Parameter Min tAVAV tAVQV tAXQX tBHQZ tBLQV tBLQX tEHQZ tELQV tELQX tGHQZ tGLQV tGLQX tPD (1) tPU (1) tRC tAA tOH tBHZ tBA tBLZ tHZ tACE tLZ tOHZ tEO tOLZ Read Cycle Time Address Valid to Output Valid Address Transition to Output Transition UBS, LBS Disable to Hi-Z Output UBS, LBS Access Time UBS, LBS Enable to Low-Z Output Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Chip Enable High to Power Down Chip Enable Low to Power Up 0 5 70 5 25 35 5 25 70 10 25 45 70 70 70 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only. Not 100% tested.
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Figure 20. SRAM Write AC Waveforms, WS Controlled with GS Low
tAVAV A0-A17 VALID tAVWH tAVEL ES tBLWH UBS, LBS tAVWL WS tWLQZ tDVWH DQ0-DQ15 INPUT VALID
AI07321
tELWH
tWHAX
tWLWH
tWHQX tWHDX
Note: Output Enable (GS) = Low.
Figure 21. SRAM Write AC Waveforms, WS Controlled with GS High
tAVAV A0-A17 VALID tAVWH tAVEL ES tBLWH UBS, LBS tAVWL WS tWLWH tELWH tWHAX
GS tDVWH DQ0-DQ15 INPUT VALID
AI07322
tWHDX
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Figure 22. SRAM Write Cycle Waveform, UBS and LBS Controlled, G Low
tAVAV A0-A17 VALID tEHAX ES tAVWH tBLWH UBS, LBS tAVWL WS tWHQX DQ0-DQ15 tWLQZ tDVWH INPUT VALID
AI07323
tWLEH
tWHDX
Figure 23. SRAM Write AC Waveforms, ES Controlled
tAVAV A0-A17 tAVEL ES tBLWH UBS, LBS tWLWH WS tDVWH DQ0-DQ15 INPUT VALID tWHDX VALID tELWH tEHAX
AI07324
Note: Output Enable (GS) = High.
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Table 24. SRAM Write AC Characteristics
SRAM Symbol Alt Parameter Min tAVAV tAVEL tAVWH tAVWL tBLWH tDVWH tEHAX tELWH, tWHAX tWHDX tWHQX tWLQZ tWLWH tWC tAS (1) tAW tAS (1) tBW tDW tWR (2) tCW (3) tWR (2) tDH tOW tWHZ tWP (4) Write Cycle Time Address Valid to Chip Enable Low Address Valid to Write Enable High Address Valid to Write Enable Low UBS, LBS Valid to End of Write Input Valid to Write Enable High Chip Enable High to Address Transition Chip Select to End of Write Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to Output Hi-Z Write Enable Pulse Width 50 30 0 60 0 0 10 25 70 0 60 0 60 70 Max ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. tAS is measured from the address valid to the beginning of write. 2. tWR is measured from the end or write to the address change. tWR applied in case a write ends as ES or WS goes High. 3. tCW is measured from ES going Low end of write. 4. A Write occurs during the overlap (t WP) of Low ES and Low WS. A write begins when ES goes Low and WS goes Low with asserting UBS or LBS for single byte operation or simultaneously asserting UBS and LBS for double byte operation. A write ends at the earliest transition when ES goes High and WS goes High. The tWP is measured from the beginning of write to the end of write.
Figure 24. SRAM Low VDDS Data Retention AC Waveforms, ES Controlled
tCDR VDDS 1.65 V VDR 1.0 V DATA RETENTION MODE tR
ES
ES VDDS - 0.2V
AI07325
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Table 25. SRAM Low VDDS Data Retention Characteristics (1, 2)
Symbol IDDDR VDR tCDR tR Parameter Supply Current (Data Retention) Supply Voltage (Data Retention) Chip Disable to Data Retention Time Operation Recovery Time Test Condition VDDS = 1.0V, ES VDDS - 0.2V no input may exceed VDDS + 2V ES VDDS - 0.2V ES VDDS - 0.2V 1 0 tRC Min Typical 0.5 Max 10 2.2 Unit A V ns ns
Note: 1. All other Inputs VIH VDDS - 0.2V or VIL 0.2V. 2. Sampled only. Not 100% tested.
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PACKAGE MECHANICAL Figure 25. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Bottom View Package Outline
D D2 D1
SE E E1 BALL "A1"
b
e
FE A
FD
SD
e A2 A1
ddd
BGA-Z12
Note: Drawing is not to scale.
Table 26. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data
Symbol A A1 A2 b D D1 D2 ddd E E1 e FD FE SD SE 8.000 5.600 0.800 1.600 1.200 0.400 0.400 - - - - - - - 0.400 12.000 5.600 8.800 0.350 - - - 0.250 1.100 0.450 - - - 0.100 - - - - - - - 0.3150 0.2205 0.0315 0.0630 0.0472 0.0157 0.0157 - - - - - - - 0.0157 0.4724 0.2205 0.3465 0.0138 - - - millimeters Typ Min Max 1.400 0.0098 0.0433 0.0177 - - - 0.0039 - - - - - - - Typ inches Min Max 0.0551
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PART NUMBERING Table 27. Ordering Information Scheme
Example: Device Type M36 = MMP (Flash + SRAM) Architecture D = Dual Bank, Page Mode Operating Voltage R = VDDF = VDDS = 1.65V to 2.2V SRAM Chip Size & Organization 4 = 4 Mbit (256Kb x 16 bit) Flash Specification Details 32A = 32 Mbit (x16), Dual Bank: 1/8-7/8 partitioning, Top Configuration 32B = 32 Mbit (x16), Dual Bank: 1/8-7/8 partitioning, Bottom Configuration SRAM Specification Details D = Asynchronous SRAM, 0.16m, 70ns speed Speed 85 = 85ns (to be characterized) 10 = 100ns 12 = 120ns Package ZA = LFBGA66: 0.8mm pitch Temperature Range 6 = -40 to 85C Option T = Tape & Reel packing M36 D R 4 32A D 10 ZA 6 T
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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APPENDIX A. BLOCK ADDRESSES Table 28. Bank A, Top Boot Block Addresses M36DR432AD
# 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Size (KWord) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 Address Range 1FF000h-1FFFFFh 1FE000h-1FEFFFh 1FD000h-1FDFFFh 1FC000h-1FCFFFh 1FB000h-1FBFFFh 1FA000h-1FAFFFh 1F9000h-1F9FFFh 1F8000h-1F8FFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 000000h-007FFFh
Table 29. Bank B, Top Boot Block Addresses M36DR432AD
# 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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Table 30. Bank B, Bottom Boot Block Addresses M36DR432BD
# 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1F8000h-1FFFFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh
Table 31. Bank A, Bottom Boot Block Addresses M36DR432BD
# 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Size (KWord) 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Address Range 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 007000h-007FFFh 006000h-006FFFh 005000h-005FFFh 004000h-004FFFh 003000h-003FFFh 002000h-002FFFh 001000h-001FFFh 000000h-000FFFh
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APPENDIX B. COMMON FLASH INTERFACE The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query Command is issued the device enters CFI Query mode and the data Table 32. Query Structure Overview
Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional)
structure is read from the memory. Tables 32, 33, 34 and 35 show the address used to retrieve each data. The Query data is always presented on the lowest order data outputs (DQ0-DQ7), the other outputs (DQ8-DQ15) are set to 0. The CFI data structure contains also a security area starting at address 81h. This area can be accessed only in read mode and it is impossible to change after it has been written by ST. Issue a Read command to return to Read mode.
Table 33. CFI Query Identification String
Offset 00h 01h 02h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0020h 00A1h - bottom 00A0h - top reserved 0051h 0052h 0059h 0002h 0000h offset = P = 0040h Address for Primary Algorithm extended Query table 0000h 0000h 0000h value = A = 0000h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (note: 0000h means none exists) Address for Alternate Algorithm extended Query table note: 0000h means none exists Manufacturer Code Device Code Reserved Query Unique ASCII String "QRY" Query Unique ASCII String "QRY" Query Unique ASCII String "QRY" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Description
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Table 34. CFI Query System Interface Information
Offset 1Bh Data 0017h Description VDDF Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDDF Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPPF [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Note: This value must be 0000h if no VPPF pin is present VPPF [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Note: This value must be 0000h if no VPPF pin is present Typical timeout per single byte/word program (multi-byte program count = 1), 2n s (if supported; 0000h = not supported) Typical timeout for maximum-size multi-byte program or page write, 2n s (if supported; 0000h = not supported) Typical timeout per individual block erase, 2n ms (if supported; 0000h = not supported) Typical timeout for full chip erase, 2n ms (if supported; 0000h = not supported) Maximum timeout for byte/word program, 2n times typical (offset 1Fh) (0000h = not supported) Maximum timeout for multi-byte program or page write, 2n times typical (offset 20h) (0000h = not supported) Maximum timeout per individual block erase, 2n times typical (offset 21h) (0000h = not supported) Maximum timeout for chip erase, 2n times typical (offset 22h) (0000h = not supported)
1Ch
0022h
1Dh
0000h
1Eh
00C0h
1Fh 20h 21h 22h 23h 24h 25h 26h
0004h 0003h 000Ah 0000h 0003h 0004h 0002h 0000h
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M36DR432AD, M36DR432BD
Table 35. Device Geometry Definition
Offset Word Mode 27h 28h 29h 2Ah 2Bh 2Ch Data 0016h 0001h 0000h 0000h 0000h 0002h Description Device Size = 2n in number of bytes Flash Device Interface Code description: Asynchronous x16 Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions within device bit 7 to 0 = x = number of Erase Block Regions Note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk." 2. x specifies the number of regions within the device containing one or more contiguous Erase Blocks of the same size. For example, a 128KB device (1Mb) having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is considered to have 5 Erase Block Regions. Even though two regions both contain 16KB blocks, the fact that they are not contiguous means they are separate Erase Block Regions. 3. By definition, symmetrically block devices have only one blocking region. M36DR432AD 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h M36DR432AD 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h M36DR432AD Erase Block Region Information 003Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h M36DR432AD 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes in size. The value z = 0 is used for 128 byte block size. e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase Block Region: e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number] y = 0 means no blocking (# blocks = y+1 = "1 block") Note: y = 0 value must be used with number of block regions of one as indicated by (x) = 0
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REVISION HISTORY Table 36. Document Revision History
Date 15-Jan-2003 15-Jan-2003 25-Feb-2003 28-Feb-2003 Version 1.0 1.1 2.0 2.1 First issue. Bottom Device Code corrected on page 1. Document promoted from Preliminary Data to full Datasheet status. VDDQF signal removed from datasheet. SRAM Input Rise and Fall Times added to, and VDDF and VDDS parameters differentiated in Table 14, Operating and AC Measurement Conditions. VDDS added to the SIGNAL DESCRIPTIONS section. Revision Details
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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